In the manufacturing process of a circuit pattern formed on the semiconductor device and the photomasks, it is difficult to avoid the occurrence of a defects such as a production failure and the adhesion of foreign materials. For this reason, the following inspection apparatuses are put to practical use: an optical pattern inspection apparatus that irradiates a target to be inspected with white light, and that then compares between circuit patterns of the same kind of a plurality of LSIs by use of an optical image to extract a defect; and a SEM pattern inspection apparatus that applies the scanning electron microscope technology, and that thereby compares circuit patterns by use of an electron-beam image, the resolution of which is higher than that of the optical image, to extract a defect.
Because the inspection speed of this SEM pattern inspection apparatus is slower than that of the optical pattern inspection apparatus, the SEM pattern inspection apparatus is so devised that instead of specifying a semiconductor chip (that is to say, all dies) on a semiconductor wafer, a die to be inspected can be specified (for example, refers to Japanese Patent Laid-Open No. 2000-162143 (FIGS. 13, 14)).
Japanese Patent Laid-Open No. 2000-162143 discloses that an operator can specify dies as an area of inspection. The image comparison checking is a method in which adjacent dies are inspected and compared in sequence. The comparing between the adjacent dies makes it possible to identify a defect. A pattern inspection method of the prior art has performed by comparing between adjacent dies, in a whole semiconductor wafer or in a part of the semiconductor wafer.